The invention relates to an elementary decoder circuit for a monolithically integrated static random access memory constructed by means of gallium arsenide field effect transistors and formed by a NOR-gate whose n inputs receive the n coded addressing signals a.sub.1, a.sub.2, . . . , a.sub.n of the memory, or their complements, its output supplying a signal which is applied to the upper transistor of a push-pull stage as well as a complementary signal which is obtained via an inverter transistor and which is applied to the lower transistor of the push-pull stage, the junction point of the two transistors of the push-pull stage supplying the word line of the memory.
The present invention is used for the construction of ultrafast cache memories for large computers used in the field of astronomy and meteorology as well as for the processors of flight simulators for the display of high-resolution digital images.
The memory circuits are almost always organized in the form of a network of cells in a matrix structure. Each cell, corresponding to a binary digit or bit, is situated at the intersection of two lines: a horizontal line or row and a vertical line or column. The lines correspond to the memory addresses and are generally denoted as X.sub.1, X.sub.2, . . . , X.sub.n for the rows and Y.sub.1, Y.sub.2, . . . , Y.sub.n for the columns. Each memory cell thus has a unique address and can be selected by simultaneous activation of the appropriate row and column. After selection of the cell, the data can be transferred to or extracted from the cell by way of a pair of lines which are common to all cells and which are referred to as bit lines.
The number of address lines required for operation of a memory having a matrix structure amounts to 2N.sup.1/2, N being the number of memory points or memory bits. Such a number of address lines would restrict the capacity of the memory; therefore, it is necessary to use a decoder circuit in order to reduce the number of address lines. For a memory which consists of 2.sup.n rows and 2.sup.p columns and whose capacity thus amounts to N=2.sup.(n+p) bits, the decoder circuit for the row addresses will comprise 2.sup.n elementary decoder circuits, each of which comprises n inputs whereto the binary coded addresses a.sub.1, a.sub.2, . . . , a.sub.n are applied, while the decoder circuit for the column addresses will comprise 2.sup.p elementary decoder circuits, each of which comprises p inputs whereto the p binary coded column addresses b.sub.1, b.sub.2, . . . , b.sub.n are applied.
Each output of the elementary decoder, or word line, carries the binary decoded signal formed by one of the 2.sup.n or 2.sup.p feasible logic combinations of said inputs.
It will be known that static random access memories differ from other types of memory on the one hand because the data can be read or written therein at random and on the other hand because the data will be sustained in the memory for as long as the power supply and the external clock signals, if any, are sustained. Therefore, the external clock signals are not obligatory.
In order to realize cache memories for the described application, use must be made of ultrafast static random access memories having a low power consumption and a monolithically integrated construction. Therefore, a technology involving gallium arsenide field effect transistors is extremely attractive for realizing such circuits, because the particularly high electronic mobility in this material enables extremely short transit times to be achieved in the transistors. Among the different technologies which can now be carried out by means of gallium arsenide transistors, the technology which is referred to as DCFL (Direct Coupled Field effect transistor Logic) is the one which offers the lowest power consumption as well as the highest integration density in combination with a very high speed. The elementary logic gate, or inverter, realized by means of this technology is composed of an enhancement-type field effect transistor (cut off voltage V.sub.T .gtoreq.0) which is associated with a load, and outputs a signal which is compatible with the input of the next logic gate.
From a publication by M. Ino et al (Musashino Electrical communication Laboratory) published in "IEEE GaAs I.C. Symposium 1982" and entitled "GaAs 1 Kb Static RAM with E/D MESFET DCFL" it is known to construct a decoder circuit for a static random access memory which is monolithically integrated on a gallium arsenide (GaAs) substrate and which is composed of field effect transistors (MESFET; Metal Semiconductor Field Effect Transistor). A decoder circuit as described in the cited document and illustrated in FIG. 1 on page 4 thereof is composed of elementary decoder circuits. Each elementary decoder is essentially formed by a NOR-gate having n inputs, each of which is intended to receive one of the binary coded address input signals a.sub.1, a.sub.2, . . . , a.sub.n, expressed in the form of a signal or its complement, formed before being input into the decoder via an intermediate circuit (Address Buffer) so as to obtain on the output of the NOR-gate a combination of binary digits produced by the logic NOR-function and forming the address of a row or a column.
This NOR-gate consists of enhancement-type gallium arsenide field effect transistors which have a cut off voltage V.sub.T .gtoreq.0, i.e. transistors which are conductive only when the voltage applied to their gate does not exceed this voltage V.sub.T. The transistors forming this NOR-gate are connected in parallel, their common source being connected to ground while their common drain is connected to the short-circuited gate-source of a depletion-type transistor which is used as the active load.
When the value of the output signal of the NOR-gate changes from 0 to 1 or from 1 to 0, the associated voltage will charge or discharge the output capacitance of the circuit. In order to obtain equivalent charging and discharging times for this capacitance, the output signal of the NOR-gate is applied to the input of an inverter stage so that the actual output signal as well as its complement are simultaneously obtained, after which each of these signals is applied to a respective input of the two inputs of a push-pull stage. The inverter stage used includes an enhancement-type transistor as the inverter transistor and a depletion-type transistor as the load. The push-pull stage also includes an enhancement-type transistor which is connected to ground in a commen source connection, in series with a depletion-type transistor which is connected to the supply voltage in a common drain connection.
According to the present state of the manufacturing technique for gallium arsenide circuits, however, the manufacturing efficiency, that is to say the percentage of circuits produced which actually operate, is very low: in the order of from 4 to 10%. After the manufacture of a circuit, the circuit is tested and must be rejected if it does not operate correctly. This low efficiency is due to the technological difficulties still encountered. Therefore, in order to improve the manufacturing efficiency of one type of circuit it is necessary to simplify the manufacture of this type of circuit.
In the case of the decoder circuit, for example it is important to replace the depletion-type transistors forming the active loads by resistive loads which are easier to realize from a technological point of view. On the other hand it is also important to replace the depletion-type transistor of the push-pull stage by an enhancement-type transistor so that only a single type of transistor need be used for the manufacture of such a circuit.
However, if only a pure and simple transposition of the circuit disclosed in the cited document is envisaged by the method described above, the following problem is also encountered: between the output of the NOR-gate and ground there is formed a parasitic diode due to the fact that the inverter transistor whereto the output voltage is applied is of the Schottky type. This parasitic diode effect prevents the output signal of the NOR-gate from reaching a sufficiently high level for the unblocking of the transistor of the push-pull stage whereto it is applied. The push-pull stage is thus rendered ineffective and in these circumstances it will be time consuming and difficult to charge the output capacitance of the elementary decoder.